CD00237391 Datasheet, PDF (138/177 Pages) STMicroelectronics – ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM

Electrical characteristics
STM32F20xxx
Table 79. Switching characteristics for PC Card/CF read and write cycles in I/O space⁽¹⁾⁽²⁾
Symbol
Parameter
Min
Max
Unit
t_w(NIOWR)
FSMC_NIOWR low width
8T_HCLK - 0.5
-
ns
t_v(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid
-
5T_HCLK- 1
ns
t_h(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid
8T_HCLK- 3
-
ns
t_{d(NCE4_1-NIOWR)} FSMC_NCE4_1 low to FSMC_NIOWR valid
-
5T_HCLK+ 1.5
ns
t_{h(NCEx-NIOWR)} FSMC_NCEx high to FSMC_NIOWR invalid
5T_HCLK
-
ns
t_{d(NIORD-NCEx)} FSMC_NCEx low to FSMC_NIORD valid
-
5T_HCLK+ 1
ns
t_{h(NCEx-NIORD)} FSMC_NCEx high to FSMC_NIORD) valid
5T_HCLK– 0.5
-
ns
t_w(NIORD)
FSMC_NIORD low width
8T_HCLK+ 1
-
ns
t_su(D-NIORD)
FSMC_D[15:0] valid before FSMC_NIORD
high
9.5
ns
t_d(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high
0
ns
1. C_L = 30 pF.
2. Based on characterization, not tested in production.
NAND controller waveforms and timings
Figure 68 through Figure 71 represent synchronous waveforms, together with Table 80 and
Table 81 provides the corresponding timings. The results shown in this table are obtained
with the following FSMC configuration:
● COM.FSMC_SetupTime = 0x01;
● COM.FSMC_WaitSetupTime = 0x03;
● COM.FSMC_HoldSetupTime = 0x02;
● COM.FSMC_HiZSetupTime = 0x01;
● ATT.FSMC_SetupTime = 0x01;
● ATT.FSMC_WaitSetupTime = 0x03;
● ATT.FSMC_HoldSetupTime = 0x02;
● ATT.FSMC_HiZSetupTime = 0x01;
● Bank = FSMC_Bank_NAND;
● MemoryDataWidth = FSMC_MemoryDataWidth_16b;
● ECC = FSMC_ECC_Enable;
● ECCPageSize = FSMC_ECCPageSize_512Bytes;
● TCLRSetupTime = 0;
● TARSetupTime = 0;
In all timing tables, the T_HCLK is the HCLK clock period.
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