CD00237391 Datasheet, PDF (23/177 Pages) STMicroelectronics – ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM

STM32F20xxx
Description
Regulator ON
The regulator ON modes are activated by default on LQFP packages.On WLCSP66
package, they are activated by connecting both REGOFF and IRROFF pins to V_SS, while
only REGOFF must be connected to V_SS on UFBGA176 package (IRROFF is not available).
V_DD minimum value is 1.8 V^(a).
There are three regulator ON modes:
● MR is used in nominal regulation mode (Run)
● LPR is used in Stop mode
● Power-down is used in Standby mode:
The regulator output is in high impedance: the kernel circuitry is powered down,
inducing zero consumption (but the contents of the registers and SRAM are lost).
Regulator OFF
● Regulator OFF/internal reset ON
On WLCSP66 package, this mode is activated by connecting REGOFF pin to V_DD and
IRROFF pin to V_SS. On UFBGA176 package, only REGOFF must be connected to V_DD
(IRROFF not available).
The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage
source through V_{CAP_1} and V_{CAP_2} pins, in addition to V_DD.
The following conditions must be respected:
– V_DD should always be higher than V_{CAP_1} and V_{CAP_2} to avoid current injection
between power domains.
– If the time for V_{CAP_1} and V_{CAP_2} to reach 1.08 V is faster than the time for V_DD to
reach 1.8 V^(a), then PA0 should be connected to the NRST pin (see Figure 6).
Otherwise, PA0 should be asserted low externally during POR until V_DD reaches
1.8 V (see Figure 7).
In this mode, PA0 cannot be used as a GPIO pin since it allows to reset the part of the
1.2 V logic which is not reset by the NRST pin, when the internal voltage regulator in
OFF.
● Regulator OFF/internal reset OFF
On WLCSP66 package, this mode activated by connecting REGOFF to V_SS and
IRROFF to V_DD. IRROFF cannot be activated in conjunction with REGOFF. This mode
is available only on the WLCSP package. It allows to supply externally a 1.2 V voltage
source through V_{CAP_1} and V_{CAP_2} pins, in addition to V_DD.
The following conditions must be respected:
– V_DD should always be higher than V_{CAP_1} and V_{CAP_2} to avoid current injection
between power domains (see Figure 6).
– PA0 should be kept low to cover both conditions: until V_{CAP_1} and V_{CAP_2} reach
1.08 V, and until V_DD reaches 1.65 V.
– NRST should be controlled by an external reset controller to keep the device
under reset when V_DD is below 1.65 V (see Figure 7).
a.
V_DD minimum value is 1.7 V when the device operates in the 0 to 70 °C temperature range
and IRROFF is set to V_DD.
Doc ID 15818 Rev 9
23/177