CD00237391 Datasheet, PDF (31/177 Pages) STMicroelectronics – ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM

STM32F20xxx
Description
2.2.27
2.2.28
2.2.29
Controller area network (CAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). The 256 bytes of SRAM which are allocated for each CAN are not shared
with any other peripheral.
Universal serial bus on-the-go full-speed (OTG_FS)
The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 1.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator. The major features are:
● Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
● Supports the session request protocol (SRP) and host negotiation protocol (HNP)
● 4 bidirectional endpoints
● 8 host channels with periodic OUT support
● HNP/SNP/IP inside (no need for any external resistor)
● For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
● Internal FS OTG PHY support
Universal serial bus on-the-go high-speed (OTG_HS)
The STM32F20x devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG
peripheral. The USB OTG HS supports both full-speed and high-speed operations. It
integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin
interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS
mode, an external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
1.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator. The major features are:
● Combined Rx and Tx FIFO size of 1024× 35 bits with dynamic FIFO sizing
● Supports the session request protocol (SRP) and host negotiation protocol (HNP)
● 6 bidirectional endpoints
● 12 host channels with periodic OUT support
● Internal FS OTG PHY support
● External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
● Internal USB DMA
● HNP/SNP/IP inside (no need for any external resistor)
● For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
Doc ID 15818 Rev 9
31/177