CD00237391 Datasheet, PDF (127/177 Pages) STMicroelectronics – ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM

STM32F20xxx
Electrical characteristics
Figure 57. Asynchronous multiplexed PSRAM/NOR write waveforms
FSMC_NEx
t_w(NE)
FSMC_NOE
FSMC_NWE
FSMC_A[25:16]
FSMC_NBL[1:0]
FSMC_AD[15:0]
t_{v(NWE_NE)}
t_w(NWE)
t_{v(A_NE)}
t_{v(BL_NE)}
t _{v(A_NE)}
Address
t _{v(NADV_NE)}
t_w(NADV)
t_{h(A_NWE)}
Address
t_{h(BL_NWE)}
NBL
t _{v(Data_NADV)}
Data
t_{h(AD_NADV)}
t _{h(NE_NWE)}
t_{h(Data_NWE)}
FSMC_NADV
ai14891B
Table 73. Asynchronous multiplexed PSRAM/NOR write timings⁽¹⁾⁽²⁾
Symbol
Parameter
Min
Max
Unit
t_w(NE)
t_{v(NWE_NE)}
t_w(NWE)
t_{h(NE_NWE)}
t_{v(A_NE)}
t_{v(NADV_NE)}
t_w(NADV)
t_{h(AD_NADV)}
FSMC_NE low time
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low tim e
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
FSMC_AD(adress) valid hold time after
FSMC_NADV high)
4T_HCLK-1
T_HCLK- 1
2T_HCLK
T_HCLK- 1
-
1
T_HCLK– 2
T_HCLK
4T_HCLK+1 ns
T_HCLK
ns
2T_HCLK+1 ns
-
ns
0
ns
2
ns
T_HCLK+ 2 ns
-
ns
t_{h(A_NWE)}
t_{h(BL_NWE)}
t_{v(BL_NE)}
t_{v(Data_NADV)}
t_{h(Data_NWE)}
Address hold time after FSMC_NWE high
FSMC_BL hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
FSMC_NADV high to Data valid
Data hold time after FSMC_NWE high
T_HCLK– 0.5
-
ns
T_HCLK- 1
-
ns
-
0.5
ns
-
T_HCLK+2 ns
T_HCLK– 0.5
-
ns
1. C_L = 30 pF.
2. Based on characterization, not tested in production.
Doc ID 15818 Rev 9
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