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CD00253742 Datasheet, PDF (93/120 Pages) STMicroelectronics – XL-density performance line ARM-based 32-bit MCU
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STM32F103xF, STM32F103xG
Electrical characteristics
I2S - SPI characteristics
Unless otherwise specified, the parameters given in Table 56 for SPI or in Table 57 for I2S
are derived from tests performed under ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 10.
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 56. SPI characteristics
Symbol
Parameter
Conditions
Min Max Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
Slave mode
-
18
MHz
-
18
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
-
8
ns
DuCy(SCK)
SPI slave input clock duty
cycle
Slave mode
30
70
%
tsu(NSS)(1) NSS setup time
Slave mode
4tPCLK
-
th(NSS)(1) NSS hold time
Slave mode
2tPCLK
-
tw(SCKH)(1)
tw(SCKL)(1)
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
50
60
tsu(MI) (1)
tsu(SI)(1)
Data input setup time
Master mode
Slave mode
5
-
5
-
th(MI) (1)
Master mode
5
Data input hold time
th(SI)(1)
Slave mode
4
ta(SO)(1)(2) Data output access time Slave mode, fPCLK = 20 MHz
0
tdis(SO)(1)(3) Data output disable time Slave mode
2
tv(SO) (1) Data output valid time Slave mode (after enable edge)
-
tv(MO)(1) Data output valid time Master mode (after enable edge) -
th(SO)(1)
th(MO)(1)
Data output hold time
Slave mode (after enable edge) 15
Master mode (after enable edge) 2
-
-
ns
3tPCLK
10
25
5
-
-
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Doc ID 16554 Rev 3
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