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CD00253742 Datasheet, PDF (104/120 Pages) STMicroelectronics – XL-density performance line ARM-based 32-bit MCU
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 56. Typical connection diagram using the ADC
RAIN(1)
AINx
VAIN
Cparasitic
VDD
VT
0.6 V
VT
0.6 V
IL±1 µA
STM32F103xx
Sample and hold ADC
converter
RADC(1)
12-bit
converter
CADC(1)
ai14150c
1. Refer to Table 62 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 57 or Figure 58,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 57. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F103xx
VREF+
(see note 1)
1 µF // 10 nF
1 µF // 10 nF
VDDA
VSSA /VREF–
(see note 1)
ai14388b
1. VREF+ and VREF– inputs are available only on 100-pin packages.
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Doc ID 16554 Rev 3