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CD00253742 Datasheet, PDF (101/120 Pages) STMicroelectronics – XL-density performance line ARM-based 32-bit MCU
◁
STM32F103xF, STM32F103xG
Electrical characteristics
5.3.19
Note:
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 62 are preliminary values derived
from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 10.
It is recommended to perform a calibration after each power-up.
Table 62. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
VDDA
VREF+
IVREF
fADC
fS(2)
Power supply
Positive reference voltage
Current on the VREF input
pin
ADC clock frequency
Sampling rate
fTRIG(2) External trigger frequency
VAIN Conversion voltage range(3)
RAIN(2) External input impedance
RADC(2)
CADC(2)
Sampling switch resistance
Internal sample and hold
capacitor
tCAL(2) Calibration time
tlat(2)
Injection trigger conversion
latency
tlatr(2)
Regular trigger conversion
latency
tS(2)
tSTAB(2)
Sampling time
Power-up time
tCONV(2)
Total conversion time
(including sampling time)
fADC = 14 MHz
See Equation 1 and
Table 63 for details
2.4
-
3.6
V
2.4
-
VDDA
V
-
160 220(1)
µA
0.6
-
0.05
-
-
-
-
-
0 (VSSA or VREF-
tied to ground)
-
-
-
14
MHz
1
MHz
823
kHz
17
1/fADC
VREF+
V
50
kΩ
-
-
1
kΩ
fADC = 14 MHz
fADC = 14 MHz
fADC = 14 MHz
fADC = 14 MHz
fADC = 14 MHz
-
-
8
pF
5.9
83
-
- 0.214
-
-
3(4)
-
- 0.143
-
-
2(4)
0.107
-
17.1
1.5
- 239.5
0
0
1
1
18
14 to 252 (tS for sampling +12.5 for
successive approximation)
µs
1/fADC
µs
1/fADC
µs
1/fADC
µs
1/fADC
µs
µs
1/fADC
1. Based on characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 3: Pinouts and pin descriptions for further details.
4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 62.
Doc ID 16554 Rev 3
101/120
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