CD00253742 Datasheet, PDF (63/120 Pages) STMicroelectronics – XL-density performance line ARM-based 32-bit MCU

STM32F103xF, STM32F103xG
Electrical characteristics
Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings⁽¹⁾
Symbol
Parameter
Min
Max
Unit
t_w(NE)
FSMC_NE low time
t_{v(NOE_NE)} FSMC_NEx low to FSMC_NOE low
t_w(NOE)
FSMC_NOE low time
t_{h(NE_NOE)} FSMC_NOE high to FSMC_NE high hold time
t_{v(A_NE)}
FSMC_NEx low to FSMC_A valid
t_{h(A_NOE)} Address hold time after FSMC_NOE high
t_{v(BL_NE)}
FSMC_NEx low to FSMC_BL valid
t_{h(BL_NOE)} FSMC_BL hold time after FSMC_NOE high
t_{su(Data_NE)} Data to FSMC_NEx high setup time
t_{su(Data_NOE)} Data to FSMC_NOEx high setup time
t_{h(Data_NOE)} Data hold time after FSMC_NOE high
t_{h(Data_NE)} Data hold time after FSMC_NEx high
t_{v(NADV_NE)} FSMC_NEx low to FSMC_NADV low
t_w(NADV)
FSMC_NADV low time
1. C_L = 15 pF.
5t_HCLK + 0.5
0.5
5t_HCLK – 1
0
-
0
-
0.5
2t_HCLK - 1
2t_HCLK - 1
0
0
-
-
5t_HCLK + 2 ns
1.5
ns
5t_HCLK + 1 ns
-
ns
3
ns
-
ns
0
ns
-
ns
-
ns
-
ns
-
ns
-
ns
0
ns
t_HCLK + 2 ns
Figure 23. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
FSMC_NEx
t_w(NE)
FSMC_NOE
FSMC_NWE
FSMC_A[25:0]
FSMC_NBL[3:0]
FSMC_D[15:0]
FSMC_NADV⁽¹⁾
t_{v(NWE_NE)}
t_w(NWE)
t_{v(A_NE)}
t_{v(BL_NE)}
t_{v(Data_NE)}
t _{v(NADV_NE)}
t_w(NADV)
t_{h(A_NWE)}
Address
t_{h(BL_NWE)}
NBL
t_{h(Data_NWE)}
Data
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
t _{h(NE_NWE)}
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