CD00253742 Datasheet, PDF (91/120 Pages) STMicroelectronics – XL-density performance line ARM-based 32-bit MCU

STM32F103xF, STM32F103xG
Electrical characteristics
5.3.17
Communications interfaces
I²C interface characteristics
Unless otherwise specified, the parameters given in Table 54 are derived from tests
performed under ambient temperature, f_PCLK1 frequency and V_DD supply voltage conditions
summarized in Table 10.
The STM32F103xC, STM32F103xD and STM32F103xESTM32F103xF and STM32F103xG
performance line I²C interface meets the requirements of the standard I²C communication
protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not
“true” open-drain. When configured as open-drain, the PMOS connected between the I/O
pin and V_DD is disabled, but is still present.
The I²C characteristics are described in Table 54. Refer also to Section 5.3.14: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 54. I²C characteristics
Symbol
Parameter
Standard mode I²C⁽¹⁾ Fast mode I²C⁽¹⁾⁽²⁾
Min
Max
Min
Max
Unit
t_w(SCLL)
t_w(SCLH)
t_su(SDA)
t_h(SDA)
t_r(SDA)
t_r(SCL)
t_f(SDA)
t_f(SCL)
t_h(STA)
t_su(STA)
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Repeated Start condition
setup time
4.7
-
4.0
-
250
-
0⁽³⁾
-
1.3
-
µs
0.6
-
100
-
0⁽⁴⁾
900⁽³⁾
-
1000 20 + 0.1C_b 300
ns
-
300
-
300
4.0
-
0.6
-
µs
4.7
-
0.6
-
t_su(STO) Stop condition setup time
4.0
-
0.6
-
μs
t_w(STO:STA)
Stop to Start condition time
(bus free)
4.7
-
1.3
-
μs
C_b
Capacitive load for each bus
line
-
400
-
400
pF
1. Guaranteed by design, not tested in production.
2.
f_PCLK1 must
achieve the
be at least 2 MHz to achieve standard
fast mode I²C frequencies and it must
mode I²C frequencies. It must be at least 4 MHz
be a multiple of 10 MHz in order to reach the I2C
to
fast
mode maximum clock speed of 400 kHz.
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
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