CD00253742 Datasheet, PDF (66/120 Pages) STMicroelectronics – XL-density performance line ARM-based 32-bit MCU

Electrical characteristics
STM32F103xF, STM32F103xG
Figure 25. Asynchronous multiplexed PSRAM/NOR write waveforms
FSMC_NEx
t_w(NE)
FSMC_NOE
FSMC_NWE
FSMC_A[25:16]
FSMC_NBL[1:0]
FSMC_AD[15:0]
FSMC_NADV
t_{v(NWE_NE)}
t_w(NWE)
t_{v(A_NE)}
t_{v(BL_NE)}
t _{v(A_NE)}
Address
t _{v(NADV_NE)}
t_w(NADV)
t_{h(A_NWE)}
Address
t_{h(BL_NWE)}
NBL
t _{v(Data_NADV)}
Data
t_{h(AD_NADV)}
t _{h(NE_NWE)}
t_{h(Data_NWE)}
ai14891B
Table 35. Asynchronous multiplexed PSRAM/NOR write timings⁽¹⁾
Symbol
Parameter
Min
Max
Unit
t_w(NE)
t_{v(NWE_NE)}
t_w(NWE)
t_{h(NE_NWE)}
t_{v(A_NE)}
t_{v(NADV_NE)}
t_w(NADV)
t_{h(AD_NADV)}
FSMC_NE low time
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
FSMC_AD (address) valid hold time after
FSMC_NADV high
t_{h(A_NWE)} Address hold time after FSMC_NWE high
t_{v(BL_NE)}
FSMC_NEx low to FSMC_BL valid
t_{h(BL_NWE)} FSMC_BL hold time after FSMC_NWE high
t_{v(Data_NADV)} FSMC_NADV high to Data valid
t_{h(Data_NWE)} Data hold time after FSMC_NWE high
1. C_L = 15 pF.
5t_HCLK + 0.5 5t_HCLK + 2 ns
t_HCLK + 1 t_HCLK + 1.5 ns
3t_HCLK + 0.5 3t_HCLK + 1 ns
t_HCLK – 0.5
-
ns
-
3.5
ns
0
1
ns
t_HCLK + 0.5 t_HCLK + 1.5 ns
t_HCLK – 0.5
-
ns
4t_HCLK – 2
-
t_HCLK – 1.5
-
t_HCLK – 0.5
-
ns
0.5
ns
-
ns
t_HCLK + 6 ns
-
ns
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Doc ID 16554 Rev 3