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CD00253742 Datasheet, PDF (106/120 Pages) STMicroelectronics – XL-density performance line ARM-based 32-bit MCU
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Electrical characteristics
STM32F103xF, STM32F103xG
5.3.20 DAC electrical specifications
Table 66. DAC characteristics
Symbol
Parameter
Min Typ
Max
Unit
Comments
VDDA
Analog supply voltage
2.4
VREF+
Reference supply voltage
2.4
VSSA
Ground
0
Resistive load vs. VSSA with
buffer ON
5
RLOAD(1)
Resistive load vs. VDDA with
buffer ON
15
RO(1)
Impedance output with buffer
OFF
-
CLOAD(1) Capacitive load
-
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer ON
0.2
DAC_OUT Higher DAC_OUT voltage
max(1)
with buffer ON
-
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer OFF
-
DAC_OUT Higher DAC_OUT voltage
max(1)
with buffer OFF
-
DAC DC current
IDDVREF+ consumption in quiescent
-
mode (Standby mode)
-
DAC DC current
IDDA
consumption in quiescent
mode (Standby mode)
-
-
3.6
V
-
3.6
V VREF+ must always be below VDDA
-
0
V
-
-
kΩ
-
-
kΩ
When the buffer is OFF, the Minimum
-
15
kΩ
resistive load between DAC_OUT
and VSS to have a 1% accuracy is
1.5 MΩ
Maximum capacitive load at
-
50
pF DAC_OUT pin (when the buffer is
ON).
It gives the maximum output
-
-
V excursion of the DAC.
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VREF+ = 3.6 V
-
VDDA – 0.2
V and (0x155) and (0xEAB) at VREF+ =
2.4 V
0.5
mV
It gives the maximum output
VREF+ –
10 mV
excursion of the DAC.
V
With no load, worst code (0x0E4) at
380
µA VREF+ = 3.6 V in terms of DC
consumption on the inputs
380
µA
With no load, middle code (0x800) on
the inputs
With no load, worst code (0xF1C) at
480
µA VREF+ = 3.6 V in terms of DC
consumption on the inputs
Differential non linearity
-
DNL(2)
Difference between two
consecutive code-1LSB)
-
±0.5
±3
LSB
Given for the DAC in 10-bit
configuration
LSB
Given for the DAC in 12-bit
configuration
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Doc ID 16554 Rev 3
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