CD00253742 Datasheet, PDF (78/120 Pages) STMicroelectronics – XL-density performance line ARM-based 32-bit MCU

Electrical characteristics
STM32F103xF, STM32F103xG
Table 41. Switching characteristics for PC Card/CF read and write cycles in I/O space
Symbol
Parameter
Min
Max
tw_(NIOWR)
tv_(NIOWR-D)
FSMC_NIOWR low width
FSMC_NIOWR low to FSMC_D[15:0] valid
th_(NIOWR-D)
FSMC_NIOWR high to FSMC_D[15:0] invalid
td_{(NCE4_1-NIOWR)} FSMC_NCE4_1 low to FSMC_NIOWR valid
th_(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid
8 THCLK
-
-
5 THCLK -
4
11THCLK -
7
-
-
5THCLK +
1
5THCLK -
2.5
-
td_(NIORD-NCEx)
th_(NCEx-NIORD)
tw_(NIORD)
tsu_(D-NIORD)
td_(NIORD-D)
FSMC_NCEx low to FSMC_NIORD valid
FSMC_NCEx high to FSMC_NIORD) valid
FSMC_NIORD low width
FSMC_D[15:0] valid before FSMC_NIORD high
FSMC_D[15:0] valid after FSMC_NIORD high
-
5THCLK -
0.5
5 THCLK -
0.5
-
8THCLK
-
28
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NAND controller waveforms and timings
Figure 36 through Figure 39 represent synchronous waveforms and Table 43 provides the
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
● COM.FSMC_SetupTime = 0x00;
● COM.FSMC_WaitSetupTime = 0x02;
● COM.FSMC_HoldSetupTime = 0x01;
● COM.FSMC_HiZSetupTime = 0x00;
● ATT.FSMC_SetupTime = 0x00;
● ATT.FSMC_WaitSetupTime = 0x02;
● ATT.FSMC_HoldSetupTime = 0x01;
● ATT.FSMC_HiZSetupTime = 0x00;
● Bank = FSMC_Bank_NAND;
● MemoryDataWidth = FSMC_MemoryDataWidth_16b;
● ECC = FSMC_ECC_Enable;
● ECCPageSize = FSMC_ECCPageSize_512Bytes;
● TCLRSetupTime = 0;
● TARSetupTime = 0;
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Doc ID 16554 Rev 3