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UPSD3212A Datasheet, PDF (72/163 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic
uPSD3212A, uPSD3212C, uPSD3212CV
I2C INTERFACE
The serial port supports the twin line I2C-bus, con-
sisting of a data line (SDA1), and a clock line
(SCL1) as shown in Figure 39. Depending on the
configuration, the SDA1 and SCL1 lines may re-
quire pull-up resistors.
These lines also function as I/O port lines if the I2C
bus is not enabled.
The system is unique because data transport,
clock generation, address recognition, and bus
control arbitration are all controlled by hardware.
The I2C serial I/O has complete autonomy in byte
handling and operates in 4 modes.
■ Master transmitter
■ Master receiver
■ Slave transmitter
■ Slave receiver
These functions are controlled by the SFRs (see
Tables 50, 51, and Table 52., page 73):
– S2CON: the control of byte handling and the
operation of 4 mode.
– S2STA: the contents of its register may also
be used as a vector to various service
routines.
– S2DAT: data shift register.
– S2ADR: slave address register. Slave
address recognition is performed by On-Chip
H/W.
Figure 39. Block Diagram of the I2C Bus Serial I/O
SDA1
SCL1
7
0
Slave Address
7
0
Shift Register
Arbitration and Sync. Logic
Bus Clock Generator
7
0
Control Register
7
0
Status Register
Table 50. Serial Control Register (S2CON)
7
6
5
4
3
2
CR2
ENII
STA
STO
ADDR
AA
AI07430
1
CR1
0
CR0
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