UPSD3212A Datasheet, PDF (106/163 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic

uPSD3212A, uPSD3212C, uPSD3212CV
PLDS
The PLDs bring programmable logic functionality
to the uPSD. After specifying the logic for the
PLDs in PSDsoft Express, the logic is pro-
grammed into the device and available upon Pow-
er-up.
Table 87. DPLD and CPLD Inputs
Input Source
Input Name
Number
of
Signals
MCU Address Bus
A15-A0
16
MCU Control Signals
PSEN, RD, WR,
ALE
4
RESET
RST
1
Power-down
PDN
1
Port A Input
Macrocells¹
PA7-PA0
8
Port B Input
Macrocells
PB7-PB0
8
Port C Input
Macrocells
PC7, PC4-PC2
4
Port D Inputs
PD2-PD1
2
Page Register
PGR7-PGR0
8
Macrocell AB
Feedback
MCELLAB.FB7-
FB0
8
Macrocell BC
Feedback
MCELLBC.FB7-
FB0
8
Flash memory
Program Status Bit
Ready/Busy
1
Note: 1. These inputs are not available in the 52-pin package.
The PSD MODULE contains two PLDs: the De-
code PLD (DPLD), and the Complex PLD (CPLD).
The PLDs are briefly discussed in the next few
paragraphs, and in more detail in Decode PLD
(DPLD), page 108, and Complex PLD
(CPLD), page 109. Figure 54., page 107 shows
the configuration of the PLDs.
The DPLD performs address decoding for Select
signals for PSD MODULE components, such as
memory, registers, and I/O ports.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the Out-
put Macrocells (OMC), Input Macrocells (IMC),
and the AND Array. The CPLD can also be used
to generate External Chip Select (ECS1-ECS2)
signals.
The AND Array is used to form product terms.
These product terms are specified using PSDsoft.
The PLD input signals consist of internal MCU sig-
nals and external inputs from the I/O ports. The in-
put signals are shown in Table 87.
The Turbo Bit in PSD MODULE
The PLDs can minimize power consumption by
switching off when inputs remain unchanged for
an extended time of about 70ns. Resetting the
Turbo Bit to '0' (Bit 3 of PMMR0) automatically
places the PLDs into standby if no inputs are
changing. Turning the Turbo Mode off increases
propagation delays while reducing power con-
sumption.
See POWER MANAGEMENT, page 122, on how
to set the Turbo Bit.
Additionally, five bits are available in PMMR2 to
block MCU control signals from entering the PLDs.
This reduces power consumption and can be used
only when these MCU control signals are not used
in PLD logic equations.
Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.
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