UPSD3212A Datasheet, PDF (146/163 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic

uPSD3212A, uPSD3212C, uPSD3212CV
Figure 75. Synchronous Clock Mode Timing – PLD
tCH
tCL
CLKIN
INPUT
REGISTERED
OUTPUT
tS
tH
tCO
AI02860
Table 125. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Slew
rate⁽¹⁾
Unit
Maximum Frequency
External Feedback
1/(t_S+t_CO)
40.0
MHz
f_MAX
Maximum Frequency
Internal Feedback (f_CNT)
1/(t_S+t_CO–10)
66.6
MHz
Maximum Frequency
Pipelined Data
1/(t_CH+t_CL)
83.3
MHz
t_S
Input Setup Time
12
+ 2 + 10
ns
t_H
Input Hold Time
0
ns
t_CH
Clock High Time
Clock Input
6
ns
t_CL
Clock Low Time
Clock Input
6
ns
t_CO
Clock to Output Delay
Clock Input
13
– 2 ns
t_ARD
CPLD Array Delay
Any
macrocell
11
+2
ns
t_MIN
Minimum Clock Period⁽²⁾
t_CH+t_CL
12
ns
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.
2. CLKIN (PD1) tCLCL = tCH + tCL.
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