UPSD3212A Datasheet, PDF (47/163 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic

Watchdog reset pulse width depends on the clock
frequency. The reset period is Tf_OSC x 12 x 2²².
The RESET pulse width is Tf_OSC x 12 x 2¹⁵.
Figure 21. RESET Pulse Width
uPSD3212A, uPSD3212C, uPSD3212CV
Reset pulse width (about 10ms at 40Mhz, about 50ms at 8Mhz)
Reset period
(1.258 second at 40Mhz)
(about 6.291 seconds at 8Mhz)
AI06823
Table 34. Watchdog Timer Clear Register (WDRST: 0A6H)
7
6
5
4
3
Reserved WDRST6 WDRST5 WDRST4 WDRST3
2
WDRST2
1
WDRST1
0
WDRST0
Table 35. Description of the WDRST Bits
Bit
Symbol
Function
7
—
Reserved
6 to 0
WDRST6 to
WDRST0
To reset Watchdog Timer, write any value beteen 00h and 7Eh to this register.
This value is loaded to the 7 most significant bits of the 22-bit counter.
For example: MOV WDRST,#1EH
Note: The Watchdog Timer (WDT) is enabled at power-up or reset and must be served or disabled.
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