UPSD3212A Datasheet, PDF (126/163 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic

uPSD3212A, uPSD3212C, uPSD3212CV
RESET TIMING AND DEVICE STATUS AT RESET
Upon Power-up, the PSD MODULE requires a Re-
set (RESET) pulse of duration t_NLNH-PO after V_CC
is steady. During this period, the device loads in-
ternal configurations, clears some of the registers
and sets the Flash memory into operating mode.
After the rising edge of Reset (RESET), the PSD
MODULE remains in the Reset Mode for an addi-
tional period, t_OPR, before the first memory access
is allowed.
The Flash memory is reset to the READ Mode
upon Power-up. Sector Select (FS0-FS3 and
CSBOOT0-CSBOOT1) must all be Low, WRITE
Strobe (WR, CNTL0) High, during Power-on
RESET for maximum security of the data contents
and to remove the possibility of a byte being writ-
ten on the first edge of WRITE Strobe (WR). Any
Flash memory WRITE cycle initiation is prevented
automatically when V_CC is below V_LKO.
Warm RESET
Once the device is up and running, the PSD MOD-
ULE can be reset with a pulse of a much shorter
duration, t_NLNH. The same t_OPR period is needed
before the device is operational after a Warm RE-
SET. Figure 67 shows the timing of the Power-up
and Warm RESET.
I/O Pin, Register and PLD Status at RESET
Table 102 shows the I/O pin, register and PLD sta-
tus during Power-on RESET, Warm RESET, and
Power-down Mode. PLD outputs are always valid
during Warm RESET, and they are valid in Power-
on RESET once the internal Configuration bits are
loaded. This loading is completed typically long
before the V_CC ramps up to operating level. Once
the PLD is active, the state of the outputs are de-
termined by the PLD equations.
Figure 67. Reset (RESET) Timing
V_CC
RESET
V_CC(min)
tNLNH-PO
Power-On Reset
tOPR
tNLNH
Warm Reset
tOPR
AI07437
Table 102. Status During Power-on RESET, Warm RESET and Power-down Mode
Port Configuration
Power-on RESET
Warm RESET
Power-down Mode
MCU I/O
Input mode
Input mode
Unchanged
PLD Output
Valid after internal PSD
configuration bits are
loaded
Valid
Depends on inputs to PLD
(addresses are blocked in
PD Mode)
Address Out
Tri-stated
Tri-stated
Not defined
Peripheral I/O
Tri-stated
Tri-stated
Tri-stated
Register
Power-on RESET
Warm RESET
Power-down Mode
PMMR0 and PMMR2
Cleared to '0'
Unchanged
Unchanged
Macrocells flip-flop status
Cleared to '0' by internal
Power-on RESET
Depends on .re and .pr
equations
Depends on .re and .pr
equations
VM Register⁽¹⁾
Initialized, based on the
selection in PSDsoft
Configuration menu
Initialized, based on the
selection in PSDsoft
Configuration menu
Unchanged
All other registers
Cleared to '0'
Cleared to '0'
Unchanged
Note: 1. The SR_cod and PeriphMode Bits in the VM Register are always cleared to '0' on Power-on RESET or Warm RESET.
126/163