UPSD3212A Datasheet, PDF (147/163 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic

uPSD3212A, uPSD3212C, uPSD3212CV
Table 126. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Slew
rate⁽¹⁾
Unit
Maximum Frequency
External Feedback
1/(t_S+t_CO)
22.2
MHz
f_MAX
Maximum Frequency
Internal Feedback (f_CNT)
1/(t_S+t_CO–10)
28.5
MHz
Maximum Frequency
Pipelined Data
1/(t_CH+t_CL)
40.0
MHz
t_S
Input Setup Time
20
+ 4 + 20
ns
t_H
Input Hold Time
0
ns
t_CH
Clock High Time
Clock Input
15
ns
t_CL
Clock Low Time
Clock Input
10
ns
t_CO
Clock to Output Delay
Clock Input
25
– 6 ns
t_ARD
CPLD Array Delay
Any
macrocell
25
+4
ns
t_MIN
Minimum Clock Period⁽²⁾
t_CH+t_CL
25
ns
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.
2. CLKIN (PD1) t_CLCL = t_CH + t_CL.
Figure 76. Asynchronous RESET / Preset
tARPW
RESET/PRESET
INPUT
REGISTER
OUTPUT
tARP
AI02864
Figure 77. Asynchronous Clock Mode Timing (Product Term Clock)
tCHA
tCLA
CLOCK
tSA tHA
INPUT
REGISTERED
OUTPUT
tCOA
AI02859
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