UPSD3212A Datasheet, PDF (148/163 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic

uPSD3212A, uPSD3212C, uPSD3212CV
Table 127. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Maximum Frequency
External Feedback
1/(t_SA+t_COA)
38.4
f_MAXA
Maximum Frequency
Internal Feedback (f_CNTA)
1/(t_SA+t_COA–10)
62.5
Maximum Frequency
Pipelined Data
1/(t_CHA+t_CLA)
71.4
t_SA
Input Setup Time
7
+2
t_HA
Input Hold Time
8
t_CHA
Clock Input High Time
9
t_CLA
Clock Input Low Time
9
t_COA
Clock to Output Delay
21
t_ARDA CPLD Array Delay
Any macrocell
11
+2
t_MINA
Minimum Clock Period
1/f_CNTA
16
Turbo
Off
+ 10
+ 10
+ 10
+ 10
Slew
Rate
–2
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
Table 128. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Maximum Frequency
External Feedback
1/(t_SA+t_COA)
21.7
f_MAXA
Maximum Frequency
Internal Feedback (f_CNTA)
1/(t_SA+t_COA–10)
27.8
Maximum Frequency
Pipelined Data
1/(t_CHA+t_CLA)
33.3
t_SA
Input Setup Time
10
+4
t_HA
Input Hold Time
12
t_CHA
Clock High Time
17
t_CLA
Clock Low Time
13
t_COA
Clock to Output Delay
36
t_ARD
CPLD Array Delay
Any macrocell
25
+4
t_MINA
Minimum Clock Period
1/f_CNTA
36
Turbo
Off
+ 20
+ 20
+ 20
+ 20
Slew
Rate
–6
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
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