UPSD3212A Datasheet, PDF (109/163 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic

uPSD3212A, uPSD3212C, uPSD3212CV
Complex PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate External Chip Select
(ECS1-ECS2), routed to Port D.
Although External Chip Select (ECS1-ECS2) can
be produced by any Output Macrocell (OMC),
these External Chip Select (ECS1-ECS2) on Port
D do not consume any Output Macrocells (OMC).
As shown in Figure 54, the CPLD has the following
blocks:
■ 20 Input Macrocells (IMC)
■ 16 Output Macrocells (OMC)
■ Macrocell Allocator
■ Product Term Allocator
■ AND Array capable of generating up to 137
product terms
■ Four I/O Ports.
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD MODULE inter-
nal data bus and can be directly accessed by the
MCU. This enables the MCU software to load data
into the Output Macrocells (OMC) or read data
from both the Input and Output Macrocells (IMC
and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
Figure 56. Macrocell and I/O Port
PRODUCT TERMS
FROM OTHER
MACROCELLS
MCU ADDRESS / DATA BUS
CPLD MACROCELLS
PRODUCT TERM
ALLOCATOR
PT PRESET
MCU DATA IN
MCU LOAD
DATA
LOAD
CONTROL
UP TO 10
PRODUCT TERMS
POLARITY
SELECT
PT
CLOCK
GLOBAL
CLOCK
CLOCK
SELECT
PT CLEAR
MACROCELL
OUT TO
MCU
PR DI LD
D/T
Q
D/T/JK FF
SELECT
CK
CL
COMB.
/REG
SELECT
CPLD
OUTPUT
MACROCELL
TO
I/O PORT
ALLOC.
PT OUTPUT ENABLE (OE)
MACROCELL FEEDBACK
I/O PORT INPUT
PT INPUT LATCH GATE/CLOCK
TO OTHER I/O PORTS
I/O PORTS
LATCHED
ADDRESS OUT
DATA
DQ
WR
MUX
CPLD OUTPUT
I/O PIN
PDR
INPUT
SELECT
DQ
DIR
WR
REG.
INPUT MACROCELLS
QD
ALE
QD
G
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