UPSD3212A Datasheet, PDF (52/163 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic

uPSD3212A, uPSD3212C, uPSD3212CV
Table 41. Timer/Counter 2 Operating Modes
Mode
T2CON
RxCLK
or
TxCLK
CP/
RL2
T2MOD T2CON P1.1
TR2 ^{DECN EXEN T2EX}
Remarks
Input Clock
Internal
External
(P1.0/T2)
0
0
1
0
16-bit
0
0
1
0
Auto-
reload
0
0
1
1
0
0
1
1
0
x reload upon overflow
1
x
↓
0
reload trigger (falling edge)
f_OSC/12
Down counting
MAX
f_OSC/24
x
1 Up counting
0
1
1
x
16-bit
Capture
0
1
1
x
0
1
x
16-bit Timer/Counter
(only up counting)
↓
Capture (TH1,TL2) →
(RCAP2H,RCAP2L)
f_OSC/12
MAX
f_OSC/24
1
x
1
x
Baud Rate
Generator
1
x
1
x
0
1
x
No Overflow Interrupt
Request (TF2)
↓
Extra External Interrupt
(Timer 2)
f_OSC/12
MAX
f_OSC/24
Off
x
x
0
x
Note: ↓ = falling edge
x
x Timer 2 stops
—
—
Table 42. Description of the T2CON Bits
Bit
Symbol
Function
7
TF2
Timer 2 Overflow Flag. Set by a Timer 2 overflow, and must be cleared by software. TF2
will not be set when either (RCLK, RCLK1)=1 or (TCLK, TCLK)=1
Timer 2 External Flag set when either a capture or reload is caused by a negative
6
EXF2
transition on T2EX and EXEN2=1. When Timer 2 Interrupt is enabled, EXF2=1 will
cause the CPU to vector to the Timer 2 Interrupt routine. EXF2 must be cleared by
software
Receive Clock Flag (UART 1). When set, causes the serial port to use Timer 2 overflow
5
RCLK^{(1) pulses for its receive clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be}
used for the receive clock
Transmit Clock Flag (UART 1). When set, causes the serial port to use Timer 2 overflow
4
TCLK^{(1) pulses for its transmit clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be}
used for the transmit clock
Timer 2 External Enable Flag. When set, allows a capture or reload to occur as a result
3
EXEN2 of a negative transition on T2EX if Timer 2 is not being used to clock the serial port.
EXEN2=0 causes Time 2 to ignore events at T2EX
2
TR2
Start/stop control for Timer 2. A logic 1 starts the timer
1
C/T2
Timer or Counter Select for Timer 2. Cleared for timer operation (input from internal
system clock, t_CPU); set for external event counter operation (negative edge triggered)
Capture/Reload Flag. When set, capture will occur on negative transition of T2EX if
0
CP/RL2
EXEN2=1. When cleared, auto-reload will occur either with TImer 2 overflows, or
negative transitions of T2EX when EXEN2=1. When either (RCLK, RCLK1)=1 or (TCLK,
TCLK)=1, this bit is ignored, and timer is forced to auto-reload on Timer 2 overflow
Note: 1. The RCLK1 and TCLK1 Bits in the PCON Register control UART 2, and have the same function as RCLK and TCLK.
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