UPSD3212A Datasheet, PDF (115/163 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic

Figure 60. Peripheral I/O Mode
RD
PSEL0
PSEL1
PSEL
VM REGISTER BIT 7
uPSD3212A, uPSD3212C, uPSD3212CV
D0 - D7
DATA BUS
PA0 - PA7
WR
AI02886
Table 89. Port Operating Modes
Port Mode
Port A⁽²⁾
Port B
MCU I/O
Yes
Yes
PLD I/O
McellAB Outputs
Yes
Yes
McellBC Outputs
No
Yes
Additional Ext. CS Outputs No
No
PLD Inputs
Yes
Yes
Address Out
Yes (A7 – 0)
Yes (A7 – 0)
Peripheral I/O
Yes
No
JTAG ISP
No
No
Note: 1. JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins.
2. Port A is not available in the 52-pin package.
3. On pins PC2, PC3, PC4 and PC7 only.
Port C
Yes
No
Yes⁽³⁾
No
Yes
No
No
Yes⁽¹⁾
Port D
Yes
No
No
Yes
Yes
No
No
No
Table 90. Port Operating Mode Settings
Mode
Defined in PSDsoft
Control Register
Setting
Direction Register
Setting
VM Register Setting
MCU I/O
Declare pins only
0
1 = output,
0 = input (Note 1)
N/A
PLD I/O
Logic equations
N/A
(Note 1)
N/A
Address Out
(Port A,B)
Declare pins only
1
1 (Note 1)
N/A
Peripheral I/O
(Port A)
Logic equations
(PSEL0 & 1)
N/A
N/A
PIO Bit = 1
Note: N/A = Not Applicable
Note: 1. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Array.
Table 91. I/O Port Latched Address Output Assignments
Port A (PA3-PA0)
Port A (PA7-PA4)
Port B (PB3-PB0)
Address a3-a0
Address a7-a4
Address a3-a0
Port B (PB7-PB4)
Address a7-a4
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