UPSD3212A Datasheet, PDF (145/163 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic

Figure 74. Input to Output Disable / Enable
uPSD3212A, uPSD3212C, uPSD3212CV
INPUT
tER
tEA
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
Table 123. CPLD Combinatorial Timing (5V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Slew
rate⁽¹⁾
Unit
t_PD(2)
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
20
+ 2 + 10 – 2 ns
t_EA
CPLD Input to CPLD Output
Enable
21
+ 10 – 2 ns
t_ER
CPLD Input to CPLD Output
Disable
21
+ 10 – 2 ns
t_ARP
CPLD Register Clear or Preset
Delay
21
+ 10 – 2 ns
t_ARPW
CPLD Register Clear or Preset
Pulse Width
10
+ 10
ns
t_ARD
CPLD Array Delay
Any
macrocell
11
+2
ns
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. t_PD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial
output (80-pin package only)
Table 124. CPLD Combinatorial Timing (3V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Slew
rate⁽¹⁾
Unit
t_PD(2)
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
40
+ 4 + 20 – 6 ns
t_EA
CPLD Input to CPLD Output
Enable
43
+ 20 – 6 ns
t_ER
CPLD Input to CPLD Output
Disable
43
+ 20 – 6 ns
t_ARP
CPLD Register Clear or
Preset Delay
40
+ 20 – 6 ns
t_ARPW
CPLD Register Clear or
Preset Pulse Width
25
+ 20
ns
t_ARD
CPLD Array Delay
Any
macrocell
25
+4
ns
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial
output (80-pin package only)
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