UPSD3212A Datasheet, PDF (143/163 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic

uPSD3212A, uPSD3212C, uPSD3212CV
Figure 73. External Data Memory WRITE Cycle
ALE
PSEN
WR
PORT 0
PORT 2
tLHLL
tWHLH
tLLWL
tWLWH
tAVLL
tLLAX
A0-A7 from
RI or DPL
tAVWL
tQVWX
tQVWH
DATA OUT
P2.0 to P2.3 or A8-A11 from DPH
tWHQX
A0-A7 from PCL
INSTR IN
A8-A11 from PCH
AI07089
Table 120. External Data Memory AC Characteristics (with the 5V MCU Module)
Symbol
Parameter⁽¹⁾
40MHz Oscillator
Min
Max
Variable Oscillator
1/t_CLCL = 24 to 40MHz
Unit
Min
Max
t_RLRH
RD pulse width
120
6t_CLCL – 30
ns
t_WLWH WR pulse width
120
6t_CLCL – 30
ns
t_LLAX2 Address hold after ALE
10
t_CLCL – 15
ns
t_RHDX RD to valid data in
75
5t_CLCL – 50 ns
t_RHDX Data hold after RD
0
0
ns
t_RHDZ Data float after RD
38
2t_CLCL – 12 ns
t_LLDV
ALE to valid data in
150
8t_CLCL – 50 ns
t_AVDV
Address to valid data in
150
9t_CLCL – 75 ns
t_LLWL
ALE to WR or RD
60
90
3t_CLCL – 15 t_CLCL + 15 ns
t_AVWL Address valid to WR or RD
70
4t_CLCL – 30
ns
t_WHLH WR or RD High to ALE High
10
40
t_CLCL – 15
t_CLCL + 15
ns
t_QVWX Data valid to WR transition
5
t_CLCL – 20
ns
t_QVWH Data set up before WR
125
7t_CLCL – 50
ns
t_WHQX Data hold after WR
5
t_CLCL – 20
ns
t_RLAZ
Address float after RD
0
0
ns
Note: 1. Conditions (in addition to those in Table 109., page 133, V_CC = 4.5 to 5.5V): V_SS = 0V; C_L for Port 0, ALE and PSEN output is 100pF;
CL for other outputs is 80pF
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