LAN9115_05 Datasheet, PDF (99/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
BITS
7-6
DESCRIPTION
BackOff Limit (BOLMT). The BOLMT bits allow the user to set its back-off limit in a relaxed or
aggressive mode. According to IEEE 802.3, the MAC has to wait for a random number [r] of slot-
times** after it detects a collision, where:
(eq.1)0 < r < ₂K
The exponent K is dependent on how many times the current frame to be transmitted has been retried,
as follows:
(eq.2)K = min (n, 10) where n is the current number of retries.
If a frame has been retried three times, then K = 3 and r= 8 slot-times maximum. If it has been retried
12 times, then K = 10, and r = 1024 slot-times maximum.
An LFSR (linear feedback shift register) 20-bit counter emulates a 20bit random number generator,
from which r is obtained. Once a collision is detected, the number of the current retry of the current
frame is used to obtain K (eq.2). This value of K translates into the number of bits to use from the
LFSR counter. If the value of K is 3, the MAC takes the value in the first three bits of the LFSR counter
and uses it to count down to zero on every slot-time. This effectively causes the MAC to wait eight
slot-times. To give the user more flexibility, the BOLMT value forces the number of bits to be used
from the LFSR counter to a predetermined value as in the table below.
BOLMT Value
2’b00
2’b01
2’b10
2’b11
# Bits Used from LFSR Counter
10
8
4
1
Thus, if the value of K = 10, the MAC will look at the BOLMT if it is 00, then use the lower ten bits of the LFSR
counter for the wait countdown. If the BOLMT is 10, then it will only use the value in the first four bits for the
wait countdown, etc.
**Slot-time = 512 bit times. (See IEEE 802.3 Spec., Secs. 4.2.3.25 and 4.4.2.1)
5
Deferral Check (DFCHK). When set, enables the deferral check in the MAC. The MAC will abort the
transmission attempt if it has deferred for more than 24,288 bit times. Deferral starts when the
transmitter is ready to transmit, but is prevented from doing so because the CRS is active. Defer time
is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and
then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts. When
reset, the deferral check is disabled in the MAC and the MAC defers indefinitely.
4
Reserved
3
Transmitter enable (TXEN). When set, the MAC’s transmitter is enabled and it will transmit frames
from the buffer onto the cable.
When reset, the MAC’s transmitter is disabled and will not transmit any frames.
2
Receiver Enable (RXEN). When set (1), the MAC’s receiver is enabled and will receive frames from
the internal PHY.
When reset, the MAC’s receiver is disabled and will not receive any frames from the internal PHY.
1-0
Reserved
5.4.2 ADDRH—MAC Address High Register
Offset:
Default Value:
2
0000FFFFh
Attribute:
Size:
R/W
32 bits
The MAC Address High register contains the upper 16-bits of the physical address of the MAC. The
contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM
Controller if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0])
SMSC LAN9115
99
DATASHEET
Revision 1.1 (05-17-05)