LAN9115_05 Datasheet, PDF (48/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

3.13.1
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
TX Buffer Format
Datasheet
TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the
TX data buffer before moving the Ethernet packet data. The TX command A and command B are 32-
bit values that are used by the LAN9115 in the handling and processing of the associated Ethernet
packet data buffer. Buffer alignment, segmentation and other packet processing parameters are
included in the command structure. The following diagram illustrates the buffer format.
Host Write
Order
31
0
1st
TX Command 'A'
2nd
TX Command 'B'
3rd
Optional offset DWORD0
.
.
.
Optional offset DWORDn
Offset + Data DWORD0
.
.
.
.
.
Last Data & PAD
Optional Pad DWORD0
.
.
.
Last
Optional Pad DWORDn
3.13.2
Figure 3.14 TX Buffer Format
Figure 3.14, "TX Buffer Format", shows the TX Buffer as it is written into the LAN9115. It should be
noted that not all of the data shown in this diagram is actually stored in the TX data FIFO. This must
be taken into account when calculating the actual TX data FIFO usage. Please refer to Section 3.13.5,
"Calculating Actual TX Data FIFO Usage," on page 52 for a detailed explanation on calculating the
actual TX data FIFO usage.
Note 3.14 The LAN9115 host bus interface supports 16-bit bus transfers; internally, all data paths are
32-bits wide. Figure 3.14 describes the host write ordering for pairs of atomic 16-bit
transactions.
TX Command Format
The TX command instructs the TX FIFO controller on handling the subsequent buffer. The command
precedes the data to be transmitted. The TX command is divided into two, 32-bit words; TX command
‘A’ and TX command ‘B’.
Revision 1.1 (05-17-05)
48
DATASHEET
SMSC LAN9115