LAN9115_05 Datasheet, PDF (85/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
5.3.12 TX_FIFO_INF—Transmit FIFO Information Register
Offset:
80h
Size:
32 bits
This register contains the free space in the transmit data FIFO and the used space in the transmit
status FIFO in the LAN9115.
BITS DESCRIPTION
31-24 Reserved
23-16
15-0
TX Status FIFO Used Space (TXSUSED). Indicates the amount of space
in DWORDS used in the TX Status FIFO.
TX Data FIFO Free Space (TDFREE). Reads the amount of space in bytes,
available in the TX data FIFO. The application should never write more data
than is available, as indicated by this value.
TYPE
RO
RO
RO
DEFAULT
-
00h
1200h
5.3.13 PMT_CTRL— Power Management Control Register
Offset:
84h
Size:
32 bits
This register controls the Power Management features. This register can be read while the
LAN9115 is in a power saving mode.
Note: The LAN9115 must always be read at least once after power-up, reset, or upon return from a
power-saving state or write operations will not function.
BITS
31:14
13-12
11
10
DESCRIPTION
RESERVED
Power Management Mode (PM_MODE) – These bits set the LAN9115 into
the appropriate Power Management mode. Special care must be taken when
modifying these bits.
Encoding:
00b – D0 (normal operation)
01b – D1 (wake-up frame and magic packet detection are enabled)
10b – D2 (can perform energy detect)
11b – RESERVED - Do not set in this mode
Note:
When the LAN9115 is in a any of the reduced power modes, a write
of any data to the BYTE_TEST register will wake-up the device. DO
NOT PERFORM WRITES TO OTHER ADDRRESSES while the
READY bit in this register is cleared.
RESERVED
PHY Reset (PHY_RST) – Writing a ‘1’ to this bit resets the PHY. The internal
logic automatically holds the PHY reset for a minimum of 100us. When the
PHY is released from reset, this bit is automatically cleared. All writes to this
bit are ignored while this bit is high.
TYPE
RO
SC
RO
SC
DEFAULT
-
00b
-
0b
SMSC LAN9115
85
DATASHEET
Revision 1.1 (05-17-05)