LAN9115_05 Datasheet, PDF (78/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

5.3.6
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
FIFO_INT—FIFO Level Interrupts
Datasheet
Offset:
68h
Size:
32 bits
This register configures the limits where the FIFO Controllers will generate system interrupts.
BITS DESCRIPTION
31-24
23-16
15-8
7-0
TX Data Available Level. The value in this field sets the level, in number
of 64 Byte blocks, at which the TX FIFO Available interrupt (TFDA) will be
generated. When the TX data FIFO free space is greater than this value a
TX FIFO Available interrupt (TDFA) will be generated.
TX Status Level. The value in this field sets the level, in number of
DWORDs, at which the TX Status FIFO Level interrupt (TSFL) will be
generated. When the TX Status FIFO used space is greater than this value
an TX Status FIFO Level interrupt (TSFL) will be generated.
RX Space Available Level. The value in this field sets the level, in number
of 64 Byte blocks, at which the RX data FIFO Level interrupt (RDFL) will be
generated. When the RX data FIFO free space is less than this value an RX
data FIFO Level interrupt (RDFL) will be generated.
RX Status Level. The value in this field sets the level, in number of
DWORDs, at which the RX Status FIFO Level interrupt (RSFL) will be
generated. When the RX Status FIFO used space is greater than this value
an RX Status FIFO Level interrupt (RSFL) will be generated.
TYPE
R/W
R/W
R/W
R/W
DEFAULT
48h
00h
00h
00h
5.3.7 RX_CFG—Receive Configuration Register
Offset:
6Ch
Size:
This register controls the LAN9115 receive engine.
32 bits
BITS
31:30
29-28
27-16
DESCRIPTION
RX End Alignment. This field specifies the alignment that must be
maintained on the last data transfer of a buffer. The LAN9115 will add
extra DWORDs of data up to the alignment specified in the table below.
The host is responsible for removing these extra DWORDs. This
mechanism can be used to maintain cache line alignment on host
processors.
Please refer to Table 5.2 for bit definitions
Note:
The desired RX End Alignment must be set before reading a
packet. The RX end alignment can be changed between reading
receive packets, but must not be changed if the packet is
partially read.
Reserved
RX DMA Count (RX_DMA_CNT). This 12-bit field indicates the amount
of data, in DWORDS, to be transferred out of the RX data FIFO before
asserting the RXD_INT. After being set, this field is decremented for each
DWORD of data that is read from the RX data FIFO. This field can be
overwritten with a new value before it reaches zero.
TYPE
R/W
RO
R/W
DEFAULT
00b
-
000h
Revision 1.1 (05-17-05)
78
DATASHEET
SMSC LAN9115