LAN9115_05 Datasheet, PDF (122/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

A[7:1]
nCS, nRD
Data Bus
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Figure 6.5 PIO Write Cycle Timing
Note: The “Data Bus” width is 16 bits
Table 6.7 PIO Write Cycle Timing
SYMBOL DESCRIPTION
MIN
t_cycle
Write Cycle Time
165
t_csl
nCS, nWR Assertion Time
32
t_csh
nCS, nWR Deassertion Time
13
t_asu
Address Setup to nCS, nWR Assertion
0
t_ah
Address Hold Time
0
t_dsu
Data Setup to nCS, nWR Deassertion
7
t_dh
Data Hold Time
0
TYP
MAX UNITS
ns
ns
ns
ns
ns
ns
ns
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
6.7
TX Data FIFO Direct PIO Writes
In this mode the upper address inputs are not decoded, and any write to the LAN9115 will write the
TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is
normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9115. Timing is
identical to a PIO write, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Revision 1.1 (05-17-05)
122
DATASHEET
SMSC LAN9115