LAN9115_05 Datasheet, PDF (124/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

6.8
Reset Timing
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
nRST
Configuration
signals
Output drive
T6.1
T6.2 T6.3
T6.4
Table 6.9 Reset Timing
PARAMETER
DESCRIPTION
T6.1
T6.2
T6.3
T6.4
Reset Pulse Width
Configuration input setup to
nRST rising
Configuration input hold after
nRST rising
Output Drive after nRST rising
MIN TYP MAX UNITS
200
us
200
ns
10
ns
16
ns
NOTES
6.9
EEPROM Timing
The following specifies the EEPROM timing requirements for the LAN9115
Revision 1.1 (05-17-05)
Figure 6.7 EEPROM Timing
124
DATASHEET
SMSC LAN9115