LAN9115_05 Datasheet, PDF (117/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
processor is required to wait the specified period of time between read operations of specific
combinations of resources. The wait period is dependant upon the combination of registers being read.
Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the
minimum wait time restriction is met. Table 6.2 also shows the number of dummy reads that are
required for back-to-back read operations. The number of BYTE_TEST reads in this table is based on
the minimum timing for Tcycle (165ns). For microprocessors with slower busses the number of reads
may be reduced as long as the total time is equal to, or greater than the time specified in the table.
Dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met.
Table 6.2 Read After Read Timing Rules
AFTER
READING...
RX Data FIFO
RX Status FIFO
TX Status FIFO
RX_DROP
WAIT FOR THIS MANY
NS…
495
495
495
660
OR PERFORM THIS MANY
READS OF BYTE_TEST…
(ASSUMING TCYC OF
165NS)
3
3
3
4
BEFORE READING...
RX_FIFO_INF
RX_FIFO_INF
TX_FIFO_INF
RX_DROP
6.2
PIO Reads
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters
in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing
diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both
of these control signals must go high between cycles for the period specified.
Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read
cycles.
A[7:1]
nCS, nRD
Data Bus
Figure 6.1 LAN9115 PIO Read Cycle Timing
Note: The “Data Bus” width is 16 bits
SMSC LAN9115
117
DATASHEET
Revision 1.1 (05-17-05)