LAN9115_05 Datasheet, PDF (81/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
BITS DESCRIPTION
16-19
15-14
TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1KB values
to a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the
space allocated by TX_FIF_SIZ, and the TX data FIFO consumes the
remaining space specified by TX_FIF_SZ. The minimum size of the TX
FIFOs is 2KB (TX data and status combined). The TX data FIFO is used for
both TX data and TX commands.
The RX Status and data FIFOs consume the remaining space, which is
equal to 16KB – TX_FIF_SIZ. See section 5.3.9.1 Allowable settings for
Configurable FIFO Memory Allocationon page 82 for more information.
Reserved
13-12
Threshold Control Bits (TR). These control the transmit threshold values
the MIL should use. These bits are used when the SF bit is reset. The host
can program the Transmit threshold by setting these bits. The intent is to
allow the MIL to transfer data to the final destination only after the threshold
value is met.
In 10Mbps mode (TTM = 1) the threshold is set as follows:
TYPE
R/W
RO
R/W
DEFAULT
5h
-
00
[13]
[12]
0
0
0
1
1
0
1
1
Threshold (DWORDS)
012h
018h
020h
028h
In 100Mbps mode (TTM = 0) the threshold is set by as follows:
[13]
[12]
0
0
0
1
1
0
1
1
Threshold (DWORDS)
020h
040h
080h
100h
11-7 Reserved
RO
-
6-5 PHY Clock Select (PHY_CLK_SEL). This field is used to switch between
the internal and external MII clocks (RX_CLK and TX_CLK). This field is
R/W
00b
encoded as follows:
[6] [5]
MII Clock Source
---------------------------------------------------
00
Internal PHY
01
External MII Port
10
Clocks Disabled
11
Internal PHY
Notes:
■ This field does not control multiplexing of the SMI port or other MII signals.
■ There are restrictions on the use of this field. Please refer to Section 3.12,
"MII Interface - External MII Switching," on page 43 for details.
SMSC LAN9115
81
DATASHEET
Revision 1.1 (05-17-05)