LAN9115_05 Datasheet, PDF (89/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
5.3.16 GPT_CNT-General Purpose Timer Current Count Register
Offset:
90h
Size:
This register reflects the current value of the GP Timer.
32 bits
BITS DESCRIPTION
31-16 Reserved
15-0 General Purpose Timer Current Count (GPT_CNT). This 16-bit field
reflects the current value of the GP Timer.
TYPE
RO
RO
DEFAULT
-
FFFFh
5.3.17 ENDIAN—Endian Control
Offset:
98h
Size:
This register controls the Endianess of the LAN9115.
32 bits
BITS DESCRIPTION
31:0 Endian. If this field is set to 0xFFFFFFFFh, the LAN9115 is configured to
operate with most host big-endian processors using a 16-bit interface. If this
field is set to anything else, the LAN9115 is configured to operate with native
16-bit Little-Endian processors.
Notes:
■ Please refer to Section 3.6.1, "Bus Writes" for additional information.
■ The value of this field is only significant when configured for 16-bit
operation.
TYPE
R/W
NASR
DEFAULT
00000000h
SMSC LAN9115
89
DATASHEET
Revision 1.1 (05-17-05)