LAN9115_05 Datasheet, PDF (72/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

5.3
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
The TX data FIFO is write only. It is aliased in 8 DWORD locations (accessed from the bus interface
as 8 pairs of atomic 16-bit accesses). The host write to any of the locations since they all access the
same TX data FIFO location and perform the same function.
System Control and Status Registers
Table 5.1, "LAN9115 Direct Address Register Map", lists the registers that are directly addressable by
the host bus.
BASE ADDRESS
+ OFFSET
50h
54h
58h
5Ch
60h
64h
68h
6Ch
70h
74h
78h
7Ch
80h
84h
88h
8Ch
90h
94h
98h
9Ch
A0h
A4h
A8h
Revision 1.1 (05-17-05)
Table 5.1 LAN9115 Direct Address Register Map
CONTROL AND STATUS REGISTERS
SYMBOL
ID_REV
IRQ_CFG
INT_STS
INT_EN
RESERVED
BYTE_TEST
FIFO_INT
RX_CFG
TX_CFG
HW_CFG
RX_DP_CTL
RX_FIFO_INF
TX_FIFO_INF
PMT_CTRL
GPIO_CFG
GPT_CFG
GPT_CNT
RESERVED
ENDIAN
FREE_RUN
RX_DROP
MAC_CSR_CMD
MAC_CSR_DATA
REGISTER NAME
Chip ID and Revision.
Main Interrupt Configuration
Interrupt Status
Interrupt Enable Register
Reserved for future use
Read-only byte order testing register
FIFO Level Interrupts
Receive Configuration
Transmit Configuration
Hardware Configuration
RX Datapath Control
Receive FIFO Information
Transmit FIFO Information
Power Management Control
General Purpose IO Configuration
General Purpose Timer Configuration
General Purpose Timer Count
Reserved for future use
ENDIAN
Free Run Counter
RX Dropped Frames Counter
MAC CSR Synchronizer Command (MAC
CSR’s are indexed through this register)
MAC CSR Synchronizer Data
72
DATASHEET
DEFAULT
See “ID_REV—
Chip ID and
Revision” on
page 73.
00000000h
00000000h
00000000h
-
87654321h
48000000h
00000000h
00000000h
00000800h
00000000h
00000000h
00001200h
00000000h
00000000h
0000FFFFh
0000FFFFh
-
00000000h
-
00000000h
00000000h
00000000h
SMSC LAN9115