LAN9115_05 Datasheet, PDF(28/131 Page) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

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LAN9115_05 Datasheet, PDF (28/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

Datasheet

Table 3.2 Wake-Up Frame Filter Register Structure

Filter 0 Byte Mask

Filter 1 Byte Mask

Filter 2 Byte Mask

Filter 3 Byte Mask

Reserved

Filter 3

Command

Reserved

Filter 2

Command

Reserved

Filter 1

Command

Reserved

Filter 0

Command

Filter 3 Offset

Filter 2 Offset

Filter 1Offset

Filter 0 Offset

Filter 1 CRC-16

Filter 0 CRC-16

Filter 3 CRC-16

Filter 2 CRC-16

The Filter i Byte Mask defines which incoming frame bytes Filter i will examine to determine whether

or not this is a wake-up frame. Table 3.3, describes the byte maskâs bit fields.

FIELD

30:0

Table 3.3 Filter i Byte Mask Bit Definitions

FILTER I BYTE MASK DESCRIPTION

DESCRIPTION

Must be zero (0)

Byte Mask: If bit j of the byte mask is set, the CRC machine processes byte number pattern - (offset

+ j) of the incoming frame. Otherwise, byte pattern - (offset + j) is ignored.

The Filter i command register controls Filter i operation. Table 3.4 shows the Filter I command register.

FIELD

2:1

Table 3.4 Filter i Command Bit Definitions

FILTER i COMMANDS

DESCRIPTION

Address Type: Defines the destination address type of the pattern. When bit is set, the pattern

applies

only to multicast frames. When bit is cleared, the pattern applies only to unicast frames.

RESERVED

Enable Filter: When bit is set, Filter i is enabled, otherwise, Filter i is disabled.

The Filter i Offset register defines the offset in the frameâs destination address field from which the

frames are examined by Filter i. Table 3.5 describes the Filter i Offset bit fields.

Revision 1.1 (05-17-05)

DATASHEET

SMSC LAN9115

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