LAN9115_05 Datasheet, PDF (104/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

BITS
2
1
0
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
DESCRIPTION
Pass Control Frames (FCPASS). When set, the MAC sets the Packet Filter bit in the Receive packet
status to indicate to the Application that a valid Pause frame has been received. The Application must
accept or discard a received frame based on the Packet Filter control bit. The MAC receives, decodes
and performs the Pause function when a valid Pause frame is received in Full-Duplex mode and when
flow control is enabled (FCE bit set). When reset, the MAC resets the Packet Filter bit in the Receive
packet status.
The MAC always passes the data of all frames it receives (including Flow Control frames) to the
Application. Frames that do not pass Address filtering, as well as frames with errors, are passed to
the Application. The Application must discard or retain the received frame’s data based on the
received frame’s STATUS field. Filtering modes (Promiscuous mode, for example) take precedence
over the FCPASS bit.
Flow Control Enable (FCEN). When set, enables the MAC Flow Control function. The MAC decodes
all incoming frames for control frames; if it receives a valid control frame (PAUSE command), it
disables the transmitter for a specified time (Decoded pause time x slot time). When reset, the MAC
flow control function is disabled; the MAC does not decode frames for control frames.
Note: Flow Control is applicable when the MAC is set in Full Duplex Mode. In Half-Duplex mode,
this bit enables the Backpressure function to control the flow of received frames to the MAC.
Flow Control Busy (FCBSY). This bit is set high whenever a pause frame or back pressure is being
transmitted. This bit should read logical 0 before writing to the Flow Control (FLOW) register. During
a transfer of Control Frame, this bit continues to be set, signifying that a frame transmission is in
progress. After the PAUSE control frame’s transmission is complete, the MAC resets to 0.
Notes:
■ When writing this register the FCBSY bit must always be zero.
■ Applications must always write a zero to this bit
5.4.9 VLAN1—VLAN1 Tag Register
Offset:
Default Value:
9
00000000h
Attribute:
Size:
R/W
32 bits
This register contains the VLAN tag field to identify VLAN1 frames. For VLAN frames the legal frame
length is increased from 1518 bytes to 1522 bytes.
BITS
31-16
15-0
DESCRIPTION
Reserved
VLAN1 Tag Identifier (VTI1). This contains the VLAN Tag field to identify the VLAN1 frames. This
field is compared with the 13th and 14th bytes of the incoming frames for VLAN1 frame detection.
If used, this register must be set to 0x8100.
Revision 1.1 (05-17-05)
104
DATASHEET
SMSC LAN9115