LAN9115_05 Datasheet, PDF (77/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
BITS
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2-0
DESCRIPTION
PHY (PHY_INT_EN)
Power Management Event Interrupt Enable (PME_INT_EN)
TX Status FIFO Overflow (TXSO_EN)
Receive Watchdog Time-out Interrupt (RWT_INT_EN)
Receiver Error Interrupt (RXE_INT_EN)
Transmitter Error Interrupt (TXE_INT_EN)
Reserved
TX Data FIFO Underrun Interrupt (TDFU_INT_EN)
TX Data FIFO Overrun Interrupt (TDFO_INT_EN)
TX Data FIFO Available Interrupt (TDFA_INT_EN)
TX Status FIFO Full Interrupt (TSFF_INT_EN)
TX Status FIFO Level Interrupt (TSFL_INT_EN)
RX Dropped Frame Interrupt Enable (RXDF_INT_EN)
RX Data FIFO Level Interrupt (RDFL_INT_EN)
RX Status FIFO Full Interrupt (RSFF_INT_EN)
RX Status FIFO Level Interrupt (RSFL_INT_EN)
GPIO [2:0] (GPIOx_INT_EN).
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DEFAULT
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
0
000
5.3.5 BYTE_TEST—Byte Order Test Register
Offset:
64h
Size:
32 bits
This register can be used to determine the byte ordering of the current configuration
BITS DESCRIPTION
31:0 Byte Test
TYPE
RO
DEFAULT
87654321h
SMSC LAN9115
77
DATASHEET
Revision 1.1 (05-17-05)