LAN9115_05 Datasheet, PDF (107/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 5.8 LAN9115 PHY Control and Status Register (continued)
PHY CONTROL AND STATUS REGISTERS
INDEX
(IN DECIMAL)
4
5
6
17
18
27
29
30
31
REGISTER NAME
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
Mode Control/Status Register
Special Modes Register
Special Control/Status Indications
Interrupt Source Register
Interrupt Mask Register
PHY Special Control/Status Register
5.5.1 Basic Control Register
Index (In Decimal):
0
Size:
16-bits
BITS DESCRIPTION
TYPE
DEFAULT
15 Reset. 1 = software reset. Bit is self-clearing. For best results, when setting RW/SC
0
this bit do not set other bits in this register.
14 Loopback. 1 = loopback mode, 0 = normal operation
RW
0
13 Speed Select. 1 = 100Mbps, 0 = 10Mbps. Ignored if Auto Negotiation is
enabled (0.12 = 1).
RW See Note 5.2
12 Auto-Negotiation Enable. 1 = enable auto-negotiate process (overrides
0.13 and 0.8) 0 = disable auto-negotiate process.
RW See Note 5.2
11 Power Down. 1 = General power down-mode, 0 = normal operation.
RW
0
Note:
After this bit is cleared, the PHY may auto-negotiate with it's
partner station. This process may take a few seconds to complete.
Once auto-negotiation is complete, bit 5 of the PHY's Basic Status
Register will be set.
10 Reserved
RO
0
9 Restart Auto-Negotiate. 1 = restart auto-negotiate process 0 = normal
RW/SC
0
operation. Bit is self-clearing.
8
Duplex Mode. 1 = full duplex, 0 = half duplex. Ignored if Auto Negotiation
RW
0
is enabled (0.12 = 1).
7 Collision Test. 1 = enable COL test, 0 = disable COL test
RW
0
SMSC LAN9115
107
DATASHEET
Revision 1.1 (05-17-05)