LAN9115_05 Datasheet, PDF (30/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

3.6
3.6.1
3.6.2
3.7
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Destination Address Source Address ……………FF FF FF FF FF FF
Datasheet
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
…CRC
It should be noted that Magic Packet detection can be performed when LAN9115 is in the D0 or D1
power states. In the D0 state, “Magic Packet” detection is enabled when the MPEN bit is set. In the
D1 state, Magic Packet detection, as well as wake-up frame detection, are automatically enabled when
the device enters the D1 state.
Host Bus Operations
Bus Writes
The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD
transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot
change during a sixteen bit write). No ordering requirements exist. The processor can access either
the low or high word first, as long as the next write is performed to the other word. If a write to the
same word is performed, the LAN9115 disregards the transfer.
Bus Reads
The host processor is required to perform two consecutive 16-bit reads to complete a single DWORD
transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot
change during a sixteen bit read). No ordering requirements exist. The processor can access either
the low or high word first, as long as the next read is performed from the other word. If a read to the
same word is performed, the data read is invalid and should be re-read. This is not a fatal error. The
LAN9115 will reset its read counters and restart a new cycle on the next read.
Big and Little Endian Support
The SMSC LAN9115 supports “Big-Endian” or “Little-Endian” processors with 16-bit bus interfaces. To
support big-endian processors, the hardware designer must explicitly invert the layout of the byte
lanes. The big-endian register must be set correctly following Table 3.7, "Byte Lane Mapping".
Additionally, please refer to Section 5.3.17, "ENDIAN—Endian Control," on page 89 for additional
information on status indication on Endian modes.
Revision 1.1 (05-17-05)
30
DATASHEET
SMSC LAN9115