LAN9115_05 Datasheet, PDF (76/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

BITS
12
11
10
9
8
7
6
5
4
3
2-0
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
DESCRIPTION
Reserved
TX Data FIFO Underrun Interrupt (TDFU). Generated when the TX data
FIFO underruns.
TX Data FIFO Overrun Interrupt (TDFO). Generated when the TX data
FIFO is full, and another write is attempted.
TX Data FIFO Available Interrupt (TDFA). Generated when the TX data
FIFO available space is greater than the programmed level.
TX Status FIFO Full Interrupt (TSFF). Generated when the TX Status
FIFO is full.
TX Status FIFO Level Interrupt (TSFL). Generated when the TX Status
FIFO reaches the programmed level.
RX Dropped Frame Interrupt (RXDF_INT). This interrupt is issued
whenever a receive frame is dropped.
RX Data FIFO Level Interrupt (RDFL). Generated when the RX FIFO
reaches the programmed level.
RX Status FIFO Full Interrupt (RSFF). Generated when the RX Status
FIFO is full.
RX Status FIFO Level Interrupt (RSFL). Generated when the RX Status
FIFO reaches the programmed level.
GPIO [2:0] (GPIOx_INT). Interrupts are generated from the GPIO’s.
These interrupts are configured through the GPIO_CFG register.
TYPE
RO
R/WC
DEFAULT
-
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
000
5.3.4 INT_EN—Interrupt Enable Register
Offset:
5Ch
Size:
32 bits
This register contains the interrupt masks for IRQ. Writing 1 to any of the bits enables the
corresponding interrupt as a source for IRQ. Bits in the INT_STS register will still reflect the status of
the interrupt source regardless of whether the source is enabled as an interrupt in this register.
BITS
31
30:26
25
24
23
22
21
20
19
DESCRIPTION
Software Interrupt (SW_INT_EN)
Reserved
TX Stopped Interrupt Enable (TXSTOP_INT_EN)
RX Stopped Interrupt Enable (RXSTOP_INT_EN)
RX Dropped Frame Counter Halfway Interrupt Enable
(RXDFH_INT_EN).
Reserved
TX IOC Interrupt Enable (TIOC_INT_EN)
RX DMA Interrupt (RXD_INT).
GP Timer (GPT_INT_EN)
TYPE
R/W
RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
DEFAULT
0
-
0
0
0
0
0
0
0
Revision 1.1 (05-17-05)
76
DATASHEET
SMSC LAN9115