LAN9115_05 Datasheet, PDF (73/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 5.1 LAN9115 Direct Address Register Map (continued)
CONTROL AND STATUS REGISTERS
BASE ADDRESS
+ OFFSET
ACh
B0h
B4h
B8h - FCh
SYMBOL
AFC_CFG
E2P_CMD
E2P_DATA
RESERVED
REGISTER NAME
Automatic Flow Control Configuration
EEPROM command (The EEPROM is
indexed through this register)
EEPROM Data
Reserved for future use
DEFAULT
00000000h
00000000h
00000000h
-
5.3.1 ID_REV—Chip ID and Revision
Offset:
50h
Size:
32 bits
This register contains the ID and Revision fields for this design.
BITS DESCRIPTION
31-16 Chip ID. This read-only field identifies this design
15-0 Chip Revision. This is the current revision of the chip.
TYPE
RO
RO
DEFAULT
0115h
0001h
5.3.2 IRQ_CFG—Interrupt Configuration Register
Offset:
54h
Size:
32 bits
This register configures and indicates the state of the IRQ signal.
BITS
31:24
23-15
DESCRIPTION
TYPE
Interrupt Deassertion Interval (INT_DEAS). This field determines the
R/W
Interrupt Deassertion Interval for the Interrupt Request in multiples of 10
microseconds.
Writing zeros to this field disables the INT_DEAS Interval and resets the
interval counter. Any pending interrupts are then issued. If a new, non-
zero value is written to the INT_DEAS field, any subsequent interrupts
will obey the new setting.
Note: The Interrupt Deassertion interval does not apply to the PME
interrupt.
Reserved
RO
DEFAULT
0
-
SMSC LAN9115
73
DATASHEET
Revision 1.1 (05-17-05)