LAN9115_05 Datasheet, PDF (100/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
is loaded from address 0x05 of the EEPROM. The second byte (bits [15:8]) is loaded from address
0x06 of the EEPROM. Please refer to Section 4.6 for more information on the EEPROM. Section 5.4.3
details the byte ordering of the ADDRL and ADDRH registers with respect to the reception of the
Ethernet physical address.
BITS
31-16
15-0
DESCRIPTION
Reserved
Physical Address [47:32]. This field contains the upper 16-bits (47:32) of the Physical Address of
the LAN9115 device. The content of this field is undefined until loaded from the EEPROM at power-
on. The host can update the contents of this field after the initialization process has completed.
5.4.3 ADDRL—MAC Address Low Register
Offset:
Default Value:
3
FFFFFFFFh
Attribute:
Size:
R/W
32 bits
The MAC Address Low register contains the lower 32 bits of the physical address of the MAC. The
contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM
Controller if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0])
is loaded from address 0x01 of the EEPROM. The most significant byte of this register is loaded from
address 0x04 of the EEPROM. Please refer to Section 4.6 for more information on the EEPROM.
BITS
31-0
DESCRIPTION
Physical Address [31:0]. This field contains the lower 32 bits (31:0) of the Physical Address of the
LAN9115 device. The content of this field is undefined until loaded from the EEPROM at power-on.
The host can update the contents of this field after the initialization process has completed.
Table 5.7 below illustrates the byte ordering of the ADDRL and ADDRH registers with respect to the
reception of the Ethernet physical address. Also shown is the correlation between the EEPROM
addresses and ADDRL and ADDRH registers.
Table 5.7 ADDRL, ADDRH and EEPROM Byte Ordering
EEPROM ADDRESS
0x01
0x02
0x03
0x04
0x05
0x06
ADDRN
ADDRL[7:0]
ADDRL[15:8]
ADDRL[23:16]
ADDRL[31:24]
ADDRH[7:0]
ADDRH[15:8]
ORDER OF RECEPTION ON
ETHERNET
1^st
2^nd
3^rd
4^th
5^th
6^th
Revision 1.1 (05-17-05)
100
DATASHEET
SMSC LAN9115