LAN9115_05 Datasheet, PDF (101/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
As an example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the ADDRL and
ADDRH registers would be programmed as shown in Figure 5.2. The values required to automatically
load this configuration from the EEPROM are also shown.
31 24 23 16 15 8 7 0
xx
xx
0xBC 0x9A
ADDRH
31 24 23 16 15 8 7
0
0x78 0x56 0x34 0x12
ADDRL
0x06 0xBC
0x05 0x9A
0x04 0x78
0x03 0x56
0x02 0x34
0x01 0x12
0x00 0xA5
EEPROM
Figure 5.2 Example ADDRL, ADDRH and EEPROM Setup
Note: By convention, the left most byte of the Ethernet address (in this example 0x12) is the most
significant byte and is transmitted/received first.
5.4.4 HASHH—Multicast Hash Table High Register
Offset:
Default Value:
4
00000000h
Attribute:
Size:
R/W
32 bits
The 64-bit Multicast table is used for group address filtering. For hash filtering, the contents of the
destination address in the incoming frame is used to index the contents of the Hash table. The most
significant bit determines the register to be used (Hi/Low), while the other five bits determine the bit
within the register. A value of 00000 selects Bit 0 of the Multicast Hash Table Lo register and a value
of 11111 selects the Bit 31 of the Multicast Hash Table Hi register.
If the corresponding bit is 1, then the multicast frame is accepted. Otherwise, it is rejected. If the “Pass All
Multicast” (MCPAS) bit is set (1), then all multicast frames are accepted regardless of the multicast hash
values.
The Multicast Hash Table Hi register contains the higher 32 bits of the hash table and the Multicast
Hash Table Low register contains the lower 32 bits of the hash table.
BITS
31-0
DESCRIPTION
Upper 32 bits of the 64-bit Hash Table
SMSC LAN9115
101
DATASHEET
Revision 1.1 (05-17-05)