LAN9115_05 Datasheet, PDF (123/131 Pages) SMSC Corporation – Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
FIFO_SEL
A[2:1]
nCS, nRD
Data Bus
Figure 6.6 TX Data FIFO Direct PIO Write Timing
Note: The “Data Bus” width is 16 bits
Table 6.8 TX Data FIFO Direct PIO Write Timing
SYMBOL
t_cycle
t_csl
t_csh
t_asu
t_ah
t_dsu
t_dh
DESCRIPTION
Write Cycle Time
nCS, nWR Assertion Time
nCS, nWR Deassertion Time
Address, FIFO_SEL Setup to nCS, nWR Assertion
Address, FIFO_SEL Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
MIN
TYP
165
32
13
0
0
7
0
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
Note: A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The
cycle ends when either or both nCS and nWR are deasserted. They may be asserted and
deasserted in any order.
SMSC LAN9115
123
DATASHEET
Revision 1.1 (05-17-05)