91C94 Datasheet, PDF (96/120 Pages) SMSC Corporation – ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM

A0-15
AEN, nSBHE
nIOCS16
nIORD
D0-15
VALID ADDRESS
t15
t4
t3
t20
t5
t6
VALID DATA ^Z
OUT
VALID ADDRESS
VALID DATA ^Z
OUT
Parameter
m in
typ
max
units
t3 Address, nSBHE, AEN Setup to Control Acti ve 25
t4 Address, nSBHE, AEN Hol d after Control
20
Inacti ve
t5 nIORD Low to Valid Data
t6 nIORD High to Data Fl oating
t15 A4-A15, AEN Low, BALE High to nIOCS16
Low
t20 Cycl e ti me*
185
ns
ns
40
ns
30
ns
25
ns
ns
BALE T ied High
IOCHRDY not used - t20 has to be met
*Note: The cycle time is defined only for consecutive accesses to the Data Register. These values assume
that IOCHRDY is not used.
FIGURE 21 - ISA CONSECUTIVE READ CYCLES
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