91C94 Datasheet, PDF (36/120 Pages) SMSC Corporation – ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM

I/O SPACE - BANK0
OFFSET
NAME
0
TRANSMIT CONTROL REGISTER
TYPE
READ/WRITE
SYMBOL
TCR
This register holds bits programmed by the CPU to control some of the protocol transmit options.
HIGH
BYTE
0
0
EPH
LOOP
STP
SQET
FDUPLX
MON_
CSN
NOCRC
X
0
0
0
0
X
0
LOW
BYTE
PAD_EN
FORCOL LOOP
TXENA
0
X
X
X
X
0
0
0
EPH_LOOP - Internal loopback at the EPH
block. Does not exercise the encoder decoder.
Serial data is looped back when set. Defaults
low. Note: After exiting the loopback test,
SRESET in Card Option Register or SOFT_RST
in RCR must be set before returning to normal
operation.
turns itself off. When this bit is clear the
transmitter ignores its own carrier. Defaults low.
NOCRC - Does not append CRC to transmitted
frames when set, allows software to insert the
desired CRC. Defaults to zero, namely CRC
inserted.
STP_SQET - Stop transmission on SQET error.
If set, stops and disables transmitter on SQE
test error. Does not stop on SQET error and
transmits next frame if clear. Defaults low.
FDUPLX - When set it enables full duplex
operation. This will cause frames to be received
if they pass the address filter regardless of the
source for the frame. When clear the node will
not receive a frame sourced by itself.
MON_CSN - When set the LAN91C94 monitors
carrier while transmitting. It must see its own
carrier by the end of the preamble. If it is not
seen, or if carrier is lost during transmission, the
transmitter aborts the frame without CRC and
PAD_EN - When set, the LAN91C94 will pad
transmit frames shorter than 64 bytes with 00.
Does not pad frames when reset.
FORCOL - When set the transmitter will force
a collision by not deferring deliberately. This bit
is set and cleared only by the CPU. When
TXENA is enabled with no packets in the queue
and while the FORCOL bit is set, the LAN91C94
will transmit a preamble pattern the next time a
carrier is seen on the line. If a packet is queued,
a preamble and SFD will be transmitted.
FORCOL defaults low to normal operation.
NOTE: The LATCOL bit in EPHSR, setting up
as a result of FORCOL, will reset TXENA to 0.
36