91C94 Datasheet, PDF (57/120 Pages) SMSC Corporation – ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM

I/O SPACE - BANK2
OFFSET
8&A
NAME
DATA REGISTER
TYPE
READ/WRITE
SYMBOL
DATA
HIGH
BYTE
DATA HIGH
LOW
BYTE
DATA LOW
DATA REGISTER - Used to read or write the
data buffer byte/word presently addressed by
the pointer register.
This register is mapped into two uni-directional
FIFOs that allow moving words to and from the
LAN91C94 regardless of whether the pointer
address is even or odd. Data goes through the
write FIFO into memory, and is pre-fetched from
memory into the read FIFO. If byte accesses
are used, the appropriate (next) byte can be
accessed through the Data Low or
Data High registers. The order to and from the
FIFO is preserved. Byte and word accesses can
be mixed on the fly in any order.
This register is mapped into two consecutive
word locations to facilitate the usage of double
word move instructions. The DATA register is
accessible at any address in the 8 through Ah
range, while the number of bytes being
transferred are determined by A0 and nSBHE in
ISA mode, and by A0, nCE1 and nCE2 in
PCMCIA mode.
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