91C94 Datasheet, PDF (100/120 Pages) SMSC Corporation – ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM

A0-15
AEN,
nSBHE
nIOCS16
VALID ADDRESS
t20
nIORD
nIOWR
t9
Z
Z
t 10
IOCHRDY
D0-D15
Z
VALI D DATA
Z
VALID ADDRESS
VALI D DATA ^Z
Paramete r
t9
Control Active to IOCHRDY Low
t10
IOCHRDY Low Pulse Width*
t20
Cycle ti me**
min
t yp
max
15
100
150
185
* Note: Assuming NO WAI T ST = 0 i n configuration register and cycle time observed.
**Note: The cycle time is defined onl y for accesses to the Data Register as foll ows:
For Data Register Read - From nIORD falling to next nIO RD falli ng
For Data Register Write - From nIOWR risi ng to next nIOWR risi ng
units
ns
ns
ns
FIGURE 25 - ISA CONSECUTIVE READ AND WRITE CYCLES
100