91C94 Datasheet, PDF (84/120 Pages) SMSC Corporation – ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM

Only when 16 retries are reached, the CSMA/CD
block will clear the TXENA bit, and CPU
intervention is required. The DMA will not
automatically restart data transfer in this case,
nor will it transmit the next enqueued packet
until TXENA is set by the CPU. The DMA will
move the packet number in question from the
TX FIFO into the TX completion FIFO.
NETWORK INTERFACE
The LAN91C94 includes both an AUI interface
for thick and thin coax applications and a
10BASE-T interface for twisted pair applications.
Functions common to both are:
1. Manchester encoder/decoder to convert
NRZ data to Manchester encoded data and
back.
2. A 32 ms jabber timer to prevent
inadvertently long transmissions. When
'jabbing' occurs, the transmitter is disabled,
automatic loopback is disabled (in 10BASE-
T mode), and a collision indication is given
to the controller. The interface 'unjabs'
when the transmitter has been idle for a
minimum of 256 ms.
3. A phase-lock loop to recover data and clock
from the Manchester data stream with up to
plus or minus 18ns of jitter.
4. Diagnostic loopback capability.
5. LED drivers for collision, transmission,
reception, and jabber.
10BASE-T
The 10BASE-T interface conforms to the twisted
pair MAU addendum to the 802.3 specification.
On the transmission side, it converts the NRZ
data from the controller to Manchester data and
provides the appropriate signal level for driving
the media. Signal are predistorted before
transmission to minimize ISI. The collision
detection circuitry monitors the simultaneous
occurrence of received signals and transmitted
data on the media. During transmission,
data is automatically looped back to the receiver
except during collision periods, in which case
the input to the receiver is network data. During
collisions, should the receive input go idle prior
to the transmitter going idle, input to the receiver
switches back to the transmitter within 9 bit
times. Following transmission, the transmitter
performs a SQE test. This test exercises the
collision detection circuitry within the 10BASE-T
interface.
The receiver monitors the media at all times. It
recovers the clock and data and passes it along
to the controller. In the absence of any receive
activity, the transmitter is looped back to the
receiver. In addition, the receiver performs
automatic polarity correction. The 10BASE-T
interface performs link integrity tests per section
14.2.1.7 of 802.3, using the following values:
1. Link_loss_timer: 64 ms
2. Link_test_min_timer: 4 ms
3. Link_count: 2
4. Link_test_max_timer: 64 ms
The state of the link is reflected in the EPHSR.
AUI
The LAN91C94 also provides a standard 6 wire
AUI interface to a coax transceiver.
PHYSICAL INTERFACE
The internal physical interface (PHY) consists of
an encoder/decoder (ENDEC) and an internal
10BASE-T transceiver. The ENDEC also
provides a standard 6-pin AUI interface to an
external coax transceiver for 10BASE-T and
10BASE-5 applications. The signals between
MAC and the PHY can be routed to pins by
asserting the nXENDEC pin low. This
feature allows the interface to an external
ENDEC and transceiver. The PHY functions
can be divided into transmit and receive
functions.
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