91C94 Datasheet, PDF (44/120 Pages) SMSC Corporation – ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM

I/O SPACE - BANK1
OFFSET
0
NAME
CONFIGURATION REGISTER
TYPE
READ/WRITE
SYMBOL
CR
The Configuration Register holds bits that define the device configuration and are not expected to
change during run-time. This register is part of the EEPROM saved setup.
HIGH
BYTE
0
NO WAIT
FULL
STEP
SET
SQLCH
AUI
SELECT
0
X
X
0
X
0
0
0
LOW
BYTE
16 BIT DIS LINK
RESERVED
INT SEL1 INT SEL0
Function of
0
1
1
0
0
0
X
nEN16 pin
NO WAIT - When set, does not request
additional wait states. An exception to this are
accesses to the Data Register if not ready for a
transfer. When clear, negates IOCHRDY for two
to three 20MHz clocks on any cycle to the
LAN91C94.
FULL STEP - This bit is used to select the
signaling mode for the AUI port. When set the
AUI port uses full step signaling. Defaults low to
half step signaling. This bit is only meaningful
when AUI SELECT is high.
SET SQLCH - When set, the squelch level used
for the 10BASE-T receive signal is 240mV.
When clear the receive squelch level is
400mV.Defaults low.
AUI SELECT - When set the AUI interface is
used, when clear the 10BASE-T interface is
used. Defaults low.
16BIT - Used in conjunction with nEN16 and
IOis8 (in PCMCIA mode only) to define the
width of the system bus. If the nEN16 pin is low,
this bit is forced high. Otherwise the bit defaults
low and can be programmed by the host CPU.
DIS LINK - This bit is used to disable the
10BASE-T link test functions. When this bit is
high the LAN91C94 disables link test functions
by not generating nor monitoring the network for
link pulses. In this mode the LAN91C94 will
transmit packets regardless of the link test, the
EPHSR LINK_OK bit will be set and the LINK
LED will stay on. When low the link test
functions are enabled. If the link status indicates
FAIL, the EPHSR LINK_OK bit will be low, while
transmit packets enqueued will be processed by
the LAN91C94, transmit data will not be sent
out to the cable.
INT SEL1-0 - Used to select one out of four
interrupt pins. The three unused interrupts are
tristated.
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